A Study on Fast Locking and Wideband PLL
نویسندگان
چکیده
In this paper , a dual-slope phase frequency detector and charge pump architecture for fast locking of PLL is proposed and analyzed. The proposed PLL circuit is designed based on the 0.11um CMOS process with 1.2V supply voltage. The modified delay cell circuit of Ring Oscillator is used in the design of VCO and the frequency range of VCO is from 23MHz to 522MHz. This frequency synthesizer has a good linearity characteristic.
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